In a single-ended delta-sigma analog-to-digital converter an error signal is integrated over time to generate an integrator response voltage that is then compared to the reference voltage, which comparison is performed with single-bit resolution at oversampling rate. The oversampled digital response of the converter is supplied to a digital decimation filter, such as afforded by a regularly read and then reset digital counter, to generate the analog-to-digital converter response at normal sampling rate. The oversampled digital response of the converter is also converted to an analog feedback signal voltage, which is differentially combined with the analog input signal voltage in generating the error signal. A commonplace practice is to obtain the analog feedback signal voltage from the output port of a data flip-flop receiving the oversampled digital response at its data input port.
A systematic error in a signed analog-to-digital conversion response occurs when the voltage at the output port of the the data flip-flop switches between two operating supply voltages that do not exactly average to the direct reference voltage. This can occur because the circuitry to develop a reference voltage midway between the two operating supply voltages is kept very simple to keep hardware costs very low. In such case the reference voltage is likely to depart from exactly the average of the data flip-flop output voltage range, which departure will appear as a systematic error in the conversion result.
In digital electronic circuit breakers or in digital electronic power meters, for example, twelve-bit accuracies are sought on the oversampled analog-to-digital converters included therein. These accuracies cannot be achieved when reference voltages are obtained by simple potential dividing circuits.